Search - crc vhdl

[Other] desigingCRCwithVDHL

Description: 用VHDL设计CRC发生器和校验器，供初学者参考。-CRC generator and calibration device for advanced users.
Platform: | Size: 112952 | Author: 小山 | Hits:

[Other resource] CRC_module_of_FPGA

Description: 利用VHDL语言编写的一个crc功能模块，可下载到FPGA实现功能-use VHDL to prepare a crc function of the module, which can be downloaded to the FPGA functions
Platform: | Size: 3030 | Author: 黎飞飞 | Hits:

Description: 可配置CRC参考设计 xilinx的ip，参考设计文档CRC_xapp562[1].pdf，VHDL语言编写的代码，包含仿真所需文件-configurable CRC Reference Design xilinx the ip, CRC_xapp562 reference design document [1]. pdf, prepared by the VHDL code The simulation includes the necessary documents
Platform: | Size: 205294 | Author: 刘超 | Hits:

[Other resource] GenCrc1

Description: 并口硬盘标准PATA6的CRC效验码的vhdl代码-Parallel hard disk standard PATA6 the CRC code well-tested code vhdl
Platform: | Size: 948 | Author: hy | Hits:

[Other resource] crc_32_16

Description: crc校验功能，用硬件语言实现，vhdl或者verilog实现。逻辑功能。-crc check function, hardware language, verilog or vhdl achieve. Logic function.
Platform: | Size: 297370 | Author: likj | Hits:

[Other] crc_pkg

Description: VHDL语言实现的CRC校验，函数形式，包括CRC4,CRC8,CRC16和CRC32
Platform: | Size: 2040 | Author: 李浩 | Hits:

[Other resource] vhdl_crc

Description: 在quartus中用VHDL语言开发的crc校验
Platform: | Size: 163894 | Author: 夏杰 | Hits:

[Other resource] ultimate_crc.tar

Description: VHDL语言实现的CRC码程序,可用于FPGA实现
Platform: | Size: 114436 | Author: 陈楚龙 | Hits:

[assembly language] GMSK_matlab

Description: gmsk的matlab实现，可直接运行，自己编写的，请高手指点！-GMSK matlab to achieve the direct running, I have written, please expert advice!
Platform: | Size: 3072 | Author: 程林强 | Hits:

[Post-TeleCom sofeware systems] crc32

Description: --循环冗余计算的并行实现代码 --初始值是全0或全1都可以-Cyclic redundancy code realize parallel computing the initial value is 0 or 1 whole can be
Platform: | Size: 1024 | Author: luvicee | Hits:

[VHDL-FPGA-Verilog] crc_verilog

Description: 循环码编码器verilog实现，里面包含有源程序和仿真图。-Cyclic code encoder Verilog realization, which contains the source code and simulation of Fig.
Platform: | Size: 15360 | Author: 萍果 | Hits:

[VHDL-FPGA-Verilog] module-Temperature

Description: DS18B20引脚功能 GND地，DQ数据总线，VDD电源电压 18B20共有三种形式的存储器资源，它们分别是： ROM 只读存储器，用于存放DS18B20ID编码，其前八位是单线系列编码，后面48位是芯片唯一的序列号，最后8位是以上56位的CRC码。DS18B20共64位ROM RAM 数据暂存器，数据掉电后丢失，共9个字节，每个字节8位，第1、2个字节是温度转换后的数据值信息，EEPROM 非易失性记忆体，用于存放长期需要保存的数据，上下限温度报警值和校验数据 -DS18B20 Function GND Ground pin, DQ data bus, VDD supply voltage 18B20 There are three forms of memory resources, they are: ROM read-only memory for storing DS18B20ID coding, the top eight single-family is encoded, followed by 48 is the chip serial number only, over the last eight is 56-bit CRC code. DS18B20 total of 64-bit ROM RAM data store, data loss after power-down, a total of 9 bytes, each byte 8-bit, 1, 2 bytes of temperature data converted value information, EEPROM non-volatile volatile memory for storage of long-term need to preserve data, upper and lower temperature alarm and calibration data
Platform: | Size: 9216 | Author: 袁亚楠 | Hits:

[VHDL-FPGA-Verilog] CRC-8

Description: VHDL code for CRC-8 computing using 32 bit input (parallel)
Platform: | Size: 1024 | Author: stefanovic | Hits:

[Documents] CRC

Description: cyclic redundency cheking for total description and also use vhdl
Platform: | Size: 273408 | Author: shyamu | Hits:

[VHDL-FPGA-Verilog] CRC

Description: 利用VHDL语言,用FPGA设计一个数据通信中常用的数据检错模块—循环冗余校验CRC模块,选用当前应用最广泛的EDA软件QUARTUS II作为开发平台-Using VHDL, FPGA design of a common data in data communication error detection module- Cyclic Redundancy Check (CRC) module, currently the most widely used EDA software QUARTUS II as a development platform
Platform: | Size: 2048 | Author: liangqing | Hits:

[Embeded-SCM Develop] 卷积码、CRC

Description: 卷积码的C源程序，包括编码器和译码器。还有一个是循环荣誉校验的vhdl]源码。-convolution of C source code, including the encoder and decoder. There is a cycle of the calibration honor VHDL] source.
Platform: | Size: 7168 | Author: signific | Hits:

[VHDL-FPGA-Verilog] CRC

Description: 赛灵思的循环冗余校验（CRC），内服详细说明-The Cyclic Redundancy Check (CRC) is a checksum technique for testing data reliability and correctness. This application note shows how to implement Configurable CRC Modules with LocalLink interfaces. Users tailor the module features to suit the protocol or application implemented in their system. The user-specified options for each of the configurable features are input parameters to the VHDL code for the modules. The VHDL source files for the CRC modules are coded using generate statements. The modules have two LocalLink interfaces: an upstream interface (US) and a downstream interface (DS)
Platform: | Size: 210944 | Author: 我是谁 | Hits:

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[Other] desigingCRCwithVDHL

[Other resource] CRC_module_of_FPGA

[Other resource] CRC_VHDL

[Other resource] GenCrc1

[Other resource] crc_32_16

[Other] crc_pkg

[Other resource] vhdl_crc

[Other resource] ultimate_crc.tar

[assembly language] GMSK_matlab

[Post-TeleCom sofeware systems] crc32

[VHDL-FPGA-Verilog] crc_verilog

[VHDL-FPGA-Verilog] module-Temperature

[VHDL-FPGA-Verilog] CRC-8

[Documents] CRC

[VHDL-FPGA-Verilog] CRC

[Embeded-SCM Develop] 卷积码、CRC

[VHDL-FPGA-Verilog] CRC

[VHDL-FPGA-Verilog] crc16

[VHDL-FPGA-Verilog] P12_CRC

[VHDL-FPGA-Verilog] Ethernet

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